#include "hb_ddr_oem.h"
#include "x3_info.h"

extern struct ddr_dfs_freqs lpddr4_samsung_1g[];
extern unsigned int lpddr4_samsung_1g_cnt;
extern struct ddr_dfs_freqs lpddr4_samsung_2g[];
extern unsigned int lpddr4_samsung_2g_cnt;
extern struct ddr_dfs_freqs lpddr4_3200_333[];
extern unsigned int lpddr4_3200_333_cnt;
/* PHY Initialize Configuration */
struct DRAM_CFG_PARAM ddr4_ddrphy_cfg[] = {
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b0_p0, TxSlewRate_DDR4_MICRON},
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b1_p0, TxSlewRate_DDR4_MICRON},
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b0_p0, TxSlewRate_DDR4_MICRON},
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b1_p0, TxSlewRate_DDR4_MICRON},
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b0_p0, TxSlewRate_DDR4_MICRON},
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b1_p0, TxSlewRate_DDR4_MICRON},
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b0_p0, TxSlewRate_DDR4_MICRON},
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b1_p0, TxSlewRate_DDR4_MICRON},
	{DWC_DDRPHYA_ANIB0__ATxSlewRate, ATxSlewRate_DDR4_MICRON},
	{DWC_DDRPHYA_ANIB1__ATxSlewRate, ATxSlewRate_DDR4_MICRON},
	{DWC_DDRPHYA_ANIB2__ATxSlewRate, ATxSlewRate_DDR4_MICRON},
	{DWC_DDRPHYA_ANIB3__ATxSlewRate, ATxSlewRate_DDR4_MICRON},
	{DWC_DDRPHYA_ANIB4__ATxSlewRate, ATxSlewRate_DDR4_MICRON_45},
	{DWC_DDRPHYA_ANIB5__ATxSlewRate, ATxSlewRate_DDR4_MICRON_45},
	{DWC_DDRPHYA_ANIB6__ATxSlewRate, ATxSlewRate_DDR4_MICRON},
	{DWC_DDRPHYA_ANIB7__ATxSlewRate, ATxSlewRate_DDR4_MICRON},
	{DWC_DDRPHYA_ANIB8__ATxSlewRate, ATxSlewRate_DDR4_MICRON},
	{DWC_DDRPHYA_ANIB9__ATxSlewRate, ATxSlewRate_DDR4_MICRON},
	{DWC_DDRPHYA_MASTER0__PllCtrl2_p0, 0x19},
	{DWC_DDRPHYA_MASTER0__ARdPtrInitVal_p0, 0x2},
	{DWC_DDRPHYA_MASTER0__DqsPreambleControl_p0, 0x9},
	{DWC_DDRPHYA_MASTER0__DbyteDllModeCntrl, 0x2},
	{DWC_DDRPHYA_MASTER0__DllLockParam_p0, 0x212},
	{DWC_DDRPHYA_MASTER0__DllGainCtl_p0, 0x61},
	{DWC_DDRPHYA_MASTER0__ProcOdtTimeCtl_p0, 0x3},
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b0_p0, TxOdtDrvStren_DDR4_MICRON},
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b1_p0, TxOdtDrvStren_DDR4_MICRON},
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b0_p0, TxOdtDrvStren_DDR4_MICRON},
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b1_p0, TxOdtDrvStren_DDR4_MICRON},
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b0_p0, TxOdtDrvStren_DDR4_MICRON},
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b1_p0, TxOdtDrvStren_DDR4_MICRON},
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b0_p0, TxOdtDrvStren_DDR4_MICRON},
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b1_p0, TxOdtDrvStren_DDR4_MICRON},
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b0_p0, TxImpedance_DDR4_MICRON},
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b1_p0, TxImpedance_DDR4_MICRON},
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b0_p0, TxImpedance_DDR4_MICRON},
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b1_p0, TxImpedance_DDR4_MICRON},
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b0_p0, TxImpedance_DDR4_MICRON},
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b1_p0, TxImpedance_DDR4_MICRON},
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b0_p0, TxImpedance_DDR4_MICRON},
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b1_p0, TxImpedance_DDR4_MICRON},
	{DWC_DDRPHYA_ANIB0__ATxImpedance, ATxImpedance_DDR4_MICRON},
	{DWC_DDRPHYA_ANIB1__ATxImpedance, ATxImpedance_DDR4_MICRON},
	{DWC_DDRPHYA_ANIB2__ATxImpedance, ATxImpedance_DDR4_MICRON},
	{DWC_DDRPHYA_ANIB3__ATxImpedance, ATxImpedance_DDR4_MICRON},
	{DWC_DDRPHYA_ANIB4__ATxImpedance, ATxImpedance_DDR4_MICRON},
	{DWC_DDRPHYA_ANIB5__ATxImpedance, ATxImpedance_DDR4_MICRON},
	{DWC_DDRPHYA_ANIB6__ATxImpedance, ATxImpedance_DDR4_MICRON},
	{DWC_DDRPHYA_ANIB7__ATxImpedance, ATxImpedance_DDR4_MICRON},
	{DWC_DDRPHYA_ANIB8__ATxImpedance, ATxImpedance_DDR4_MICRON},
	{DWC_DDRPHYA_ANIB9__ATxImpedance, ATxImpedance_DDR4_MICRON},
	{DWC_DDRPHYA_MASTER0__DfiMode, 0x5},
	{DWC_DDRPHYA_MASTER0__DfiCAMode, 0x2},
	{DWC_DDRPHYA_MASTER0__CalDrvStr0, 0x0},
	{DWC_DDRPHYA_MASTER0__CalVRefs, 0x2},
	{DWC_DDRPHYA_MASTER0__CalUclkInfo_p0, 0x320},
	{DWC_DDRPHYA_MASTER0__CalRate, 0x9},
	{DWC_DDRPHYA_MASTER0__VrefInGlobal_p0, VrefInGlobal_DDR4_MICRON},
	{DWC_DDRPHYA_DBYTE0__DqDqsRcvCntrl_b0_p0, 0x5b1},
	{DWC_DDRPHYA_DBYTE0__DqDqsRcvCntrl_b1_p0, 0x5b1},
	{DWC_DDRPHYA_DBYTE1__DqDqsRcvCntrl_b0_p0, 0x5b1},
	{DWC_DDRPHYA_DBYTE1__DqDqsRcvCntrl_b1_p0, 0x5b1},
	{DWC_DDRPHYA_DBYTE2__DqDqsRcvCntrl_b0_p0, 0x5b1},
	{DWC_DDRPHYA_DBYTE2__DqDqsRcvCntrl_b1_p0, 0x5b1},
	{DWC_DDRPHYA_DBYTE3__DqDqsRcvCntrl_b0_p0, 0x5b1},
	{DWC_DDRPHYA_DBYTE3__DqDqsRcvCntrl_b1_p0, 0x5b1},
	{DWC_DDRPHYA_MASTER0__DfiFreqRatio_p0, 0x1},
	{DWC_DDRPHYA_MASTER0__TristateModeCA_p0, 0x4},
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat0, 0x5555},
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat1, 0x5555},
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat2, 0x5555},
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat3, 0x5555},
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat4, 0x5555},
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat5, 0x5555},
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat6, 0x5555},
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat7, 0xf000},
	{DWC_DDRPHYA_MASTER0__MasterX4Config, 0x0},
#if ( RD_DBI_EN == 1 )
	{DWC_DDRPHYA_MASTER0__DMIPinPresent_p0, 0x1},
#else
	{DWC_DDRPHYA_DBYTE0__DqDqsRcvCntrl1, 0x500},
	{DWC_DDRPHYA_DBYTE1__DqDqsRcvCntrl1, 0x500},
	{DWC_DDRPHYA_DBYTE2__DqDqsRcvCntrl1, 0x500},
	{DWC_DDRPHYA_DBYTE3__DqDqsRcvCntrl1, 0x500},
	{DWC_DDRPHYA_MASTER0__DMIPinPresent_p0, 0x0},
#endif
	{DWC_DDRPHYA_MASTER0__Acx4AnibDis, 0x0},
	#ifdef ENABLE_DDR_CUSTOMER_SETTINGS
	//Add DDR4 phy default setting customization here
	#endif
};

uint32_t get_sizeof_ddr4_ddrphy_cfg(void)
{
	return ARRAY_SIZE(ddr4_ddrphy_cfg);
}

struct DRAM_CFG_PARAM ddr4_ddrphy_samsung_cfg[] = {
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b0_p0, TxSlewRate_DDR4_SAMSUNG},
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b1_p0, TxSlewRate_DDR4_SAMSUNG},
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b0_p0, TxSlewRate_DDR4_SAMSUNG},
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b1_p0, TxSlewRate_DDR4_SAMSUNG},
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b0_p0, TxSlewRate_DDR4_SAMSUNG},
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b1_p0, TxSlewRate_DDR4_SAMSUNG},
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b0_p0, TxSlewRate_DDR4_SAMSUNG},
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b1_p0, TxSlewRate_DDR4_SAMSUNG},
	{DWC_DDRPHYA_ANIB0__ATxSlewRate, ATxSlewRate_DDR4_SAMSUNG},
	{DWC_DDRPHYA_ANIB1__ATxSlewRate, ATxSlewRate_DDR4_SAMSUNG},
	{DWC_DDRPHYA_ANIB2__ATxSlewRate, ATxSlewRate_DDR4_SAMSUNG},
	{DWC_DDRPHYA_ANIB3__ATxSlewRate, ATxSlewRate_DDR4_SAMSUNG},
	{DWC_DDRPHYA_ANIB4__ATxSlewRate, ATxSlewRate_DDR4_SAMSUNG_45},
	{DWC_DDRPHYA_ANIB5__ATxSlewRate, ATxSlewRate_DDR4_SAMSUNG_45},
	{DWC_DDRPHYA_ANIB6__ATxSlewRate, ATxSlewRate_DDR4_SAMSUNG},
	{DWC_DDRPHYA_ANIB7__ATxSlewRate, ATxSlewRate_DDR4_SAMSUNG},
	{DWC_DDRPHYA_ANIB8__ATxSlewRate, ATxSlewRate_DDR4_SAMSUNG},
	{DWC_DDRPHYA_ANIB9__ATxSlewRate, ATxSlewRate_DDR4_SAMSUNG},
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b0_p0, TxOdtDrvStren_DDR4_SAMSUNG},
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b1_p0, TxOdtDrvStren_DDR4_SAMSUNG},
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b0_p0, TxOdtDrvStren_DDR4_SAMSUNG},
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b1_p0, TxOdtDrvStren_DDR4_SAMSUNG},
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b0_p0, TxOdtDrvStren_DDR4_SAMSUNG},
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b1_p0, TxOdtDrvStren_DDR4_SAMSUNG},
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b0_p0, TxOdtDrvStren_DDR4_SAMSUNG},
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b1_p0, TxOdtDrvStren_DDR4_SAMSUNG},
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b0_p0, TxImpedance_DDR4_SAMSUNG},
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b1_p0, TxImpedance_DDR4_SAMSUNG},
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b0_p0, TxImpedance_DDR4_SAMSUNG},
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b1_p0, TxImpedance_DDR4_SAMSUNG},
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b0_p0, TxImpedance_DDR4_SAMSUNG},
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b1_p0, TxImpedance_DDR4_SAMSUNG},
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b0_p0, TxImpedance_DDR4_SAMSUNG},
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b1_p0, TxImpedance_DDR4_SAMSUNG},
	{DWC_DDRPHYA_ANIB0__ATxImpedance, ATxImpedance_DDR4_SAMSUNG},
	{DWC_DDRPHYA_ANIB1__ATxImpedance, ATxImpedance_DDR4_SAMSUNG},
	{DWC_DDRPHYA_ANIB2__ATxImpedance, ATxImpedance_DDR4_SAMSUNG},
	{DWC_DDRPHYA_ANIB3__ATxImpedance, ATxImpedance_DDR4_SAMSUNG},
	{DWC_DDRPHYA_ANIB4__ATxImpedance, ATxImpedance_DDR4_SAMSUNG},
	{DWC_DDRPHYA_ANIB5__ATxImpedance, ATxImpedance_DDR4_SAMSUNG},
	{DWC_DDRPHYA_ANIB6__ATxImpedance, ATxImpedance_DDR4_SAMSUNG},
	{DWC_DDRPHYA_ANIB7__ATxImpedance, ATxImpedance_DDR4_SAMSUNG},
	{DWC_DDRPHYA_ANIB8__ATxImpedance, ATxImpedance_DDR4_SAMSUNG},
	{DWC_DDRPHYA_ANIB9__ATxImpedance, ATxImpedance_DDR4_SAMSUNG},
	{DWC_DDRPHYA_MASTER0__VrefInGlobal_p0, VrefInGlobal_DDR4_SAMSUNG},
};

uint32_t get_sizeof_ddr4_ddrphy_samsung_cfg(void)
{
	return ARRAY_SIZE(ddr4_ddrphy_samsung_cfg);
}

#define DDR4_DDRPHY_PARAM_GERNERATE(VENDOR,PARAM) \
struct DRAM_CFG_PARAM ddr4_ddrphy_cfg_##VENDOR##_##PARAM[] = { \
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b0_p0, TxSlewRate_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b1_p0, TxSlewRate_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b0_p0, TxSlewRate_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b1_p0, TxSlewRate_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b0_p0, TxSlewRate_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b1_p0, TxSlewRate_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b0_p0, TxSlewRate_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b1_p0, TxSlewRate_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_ANIB0__ATxSlewRate, ATxSlewRate_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_ANIB1__ATxSlewRate, ATxSlewRate_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_ANIB2__ATxSlewRate, ATxSlewRate_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_ANIB3__ATxSlewRate, ATxSlewRate_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_ANIB4__ATxSlewRate, ATxSlewRate_DDR4_##VENDOR##_45_##PARAM},\
	{DWC_DDRPHYA_ANIB5__ATxSlewRate, ATxSlewRate_DDR4_##VENDOR##_45_##PARAM},\
	{DWC_DDRPHYA_ANIB6__ATxSlewRate, ATxSlewRate_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_ANIB7__ATxSlewRate, ATxSlewRate_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_ANIB8__ATxSlewRate, ATxSlewRate_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_ANIB9__ATxSlewRate, ATxSlewRate_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b0_p0, TxOdtDrvStren_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b1_p0, TxOdtDrvStren_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b0_p0, TxOdtDrvStren_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b1_p0, TxOdtDrvStren_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b0_p0, TxOdtDrvStren_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b1_p0, TxOdtDrvStren_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b0_p0, TxOdtDrvStren_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b1_p0, TxOdtDrvStren_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b0_p0, TxImpedance_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b1_p0, TxImpedance_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b0_p0, TxImpedance_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b1_p0, TxImpedance_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b0_p0, TxImpedance_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b1_p0, TxImpedance_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b0_p0, TxImpedance_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b1_p0, TxImpedance_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_ANIB0__ATxImpedance, ATxImpedance_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_ANIB1__ATxImpedance, ATxImpedance_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_ANIB2__ATxImpedance, ATxImpedance_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_ANIB3__ATxImpedance, ATxImpedance_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_ANIB4__ATxImpedance, ATxImpedance_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_ANIB5__ATxImpedance, ATxImpedance_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_ANIB6__ATxImpedance, ATxImpedance_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_ANIB7__ATxImpedance, ATxImpedance_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_ANIB8__ATxImpedance, ATxImpedance_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_ANIB9__ATxImpedance, ATxImpedance_DDR4_##VENDOR##_##PARAM},\
	{DWC_DDRPHYA_MASTER0__VrefInGlobal_p0, VrefInGlobal_DDR4_SAMSUNG},\
};

DDR4_DDRPHY_PARAM_GERNERATE(SAMSUNG,D4S512M_S24_A3);
DDR4_DDRPHY_PARAM_GERNERATE(SAMSUNG,D4S512M_S2640_A3);

/* PHY Initialize Configuration */
struct DRAM_CFG_PARAM ddr4_3200_ddrphy_cfg[] = {
	{DWC_DDRPHYA_MASTER0__CalDrvStr0, 0x11},
#if ( (WR_PRE_2T == 1) && (RD_PRE_2T == 1) )
	{DWC_DDRPHYA_MASTER0__DqsPreambleControl_p0, 0x10b},
	{DWC_DDRPHYA_MASTER0__ProcOdtTimeCtl_p0, 0x3},
#elif ( (WR_PRE_2T == 0) && (RD_PRE_2T == 1) )
	{DWC_DDRPHYA_MASTER0__DqsPreambleControl_p0, 0x109},
	{DWC_DDRPHYA_MASTER0__ProcOdtTimeCtl_p0, 0x3},
#elif ( (WR_PRE_2T == 1) && (RD_PRE_2T == 0) )
	{DWC_DDRPHYA_MASTER0__DqsPreambleControl_p0, 0x10a},
	{DWC_DDRPHYA_MASTER0__ProcOdtTimeCtl_p0, 0x7},
#else
	{DWC_DDRPHYA_MASTER0__DqsPreambleControl_p0, 0x108},
	{DWC_DDRPHYA_MASTER0__ProcOdtTimeCtl_p0, 0x7},
#endif
	{DWC_DDRPHYA_MASTER0__CalUclkInfo_p0, 0x320},
	#ifdef ENABLE_DDR_CUSTOMER_SETTINGS
	//Add DDR4 phy 3200 customization here
	#endif
};

uint32_t get_sizeof_ddr4_3200_ddrphy_cfg(void)
{
	return ARRAY_SIZE(ddr4_3200_ddrphy_cfg);
}

/* PHY Initialize Configuration */
struct DRAM_CFG_PARAM ddr4_2666_ddrphy_cfg[] = {
#if ( (WR_PRE_2T == 1) && (RD_PRE_2T == 1) )
	{DWC_DDRPHYA_MASTER0__DqsPreambleControl_p0, 0x10b},
	{DWC_DDRPHYA_MASTER0__CalDrvStr0, 0x11},
	{DWC_DDRPHYA_MASTER0__ProcOdtTimeCtl_p0, 0x3},
#elif ( (WR_PRE_2T == 0) && (RD_PRE_2T == 1) )
	{DWC_DDRPHYA_MASTER0__DqsPreambleControl_p0, 0x109},
	{DWC_DDRPHYA_MASTER0__CalDrvStr0, 0x11},
	{DWC_DDRPHYA_MASTER0__ProcOdtTimeCtl_p0, 0x3},
#elif ( (WR_PRE_2T == 1) && (RD_PRE_2T == 0) )
	{DWC_DDRPHYA_MASTER0__DqsPreambleControl_p0, 0x10a},
	{DWC_DDRPHYA_MASTER0__CalDrvStr0, 0x0},
	{DWC_DDRPHYA_MASTER0__ProcOdtTimeCtl_p0, 0x7},
#else
	{DWC_DDRPHYA_MASTER0__DqsPreambleControl_p0, 0x108},
	{DWC_DDRPHYA_MASTER0__CalDrvStr0, 0x11},
	{DWC_DDRPHYA_MASTER0__ProcOdtTimeCtl_p0, 0x7},
#endif
	{DWC_DDRPHYA_MASTER0__CalUclkInfo_p0, 0x29b},
	#ifdef ENABLE_DDR_CUSTOMER_SETTINGS
	//Add DDR4 phy 2666 customization here
	#endif
};

uint32_t get_sizeof_ddr4_2666_ddrphy_cfg(void)
{
	return ARRAY_SIZE(ddr4_2666_ddrphy_cfg);
}

struct DRAM_CFG_PARAM ddr4_2640_ddrphy_cfg[] = {
#if ( (WR_PRE_2T == 1) && (RD_PRE_2T == 1) )
	{DWC_DDRPHYA_MASTER0__DqsPreambleControl_p0, 0x0b},
	{DWC_DDRPHYA_MASTER0__CalDrvStr0, 0x11},
	{DWC_DDRPHYA_MASTER0__ProcOdtTimeCtl_p0, 0x3},
#else
	//not support
#endif
	{DWC_DDRPHYA_MASTER0__CalUclkInfo_p0, 0x294},
	#ifdef ENABLE_DDR_CUSTOMER_SETTINGS
	//Add DDR4 phy 2640 customization here
	#endif
};

uint32_t get_sizeof_ddr4_2640_ddrphy_cfg(void)
{
	return ARRAY_SIZE(ddr4_2640_ddrphy_cfg);
}

/* PHY Initialize Configuration */
struct DRAM_CFG_PARAM ddr4_2400_ddrphy_cfg[] = {
	{DWC_DDRPHYA_MASTER0__PllCtrl2_p0, 0xa},
	{DWC_DDRPHYA_MASTER0__ProcOdtTimeCtl_p0, 0x2},
	{DWC_DDRPHYA_MASTER0__CalUclkInfo_p0, 0x258},
	{DWC_DDRPHYA_MASTER0__CalDrvStr0, 0x11},
	#ifdef ENABLE_DDR_CUSTOMER_SETTINGS
	//Add DDR4 phy 2400 customization here
	#endif
};

uint32_t get_sizeof_ddr4_2400_ddrphy_cfg(void)
{
	return ARRAY_SIZE(ddr4_2400_ddrphy_cfg);
}

struct DRAM_CFG_PARAM ddr4_1600_ddrphy_cfg[] = {
	{DWC_DDRPHYA_MASTER0__PllCtrl2_p0, 0xb},
	{DWC_DDRPHYA_MASTER0__ARdPtrInitVal_p0, 0x1},
	{DWC_DDRPHYA_MASTER0__ProcOdtTimeCtl_p0, 0xa},
	{DWC_DDRPHYA_MASTER0__CalUclkInfo_p0, 0x190},
	#ifdef ENABLE_DDR_CUSTOMER_SETTINGS
	//Add DDR4 phy 1600 customization here
	#endif
};

uint32_t get_sizeof_ddr4_1600_ddrphy_cfg(void)
{
	return ARRAY_SIZE(ddr4_1600_ddrphy_cfg);
}

struct DRAM_CFG_PARAM lpddr4_ddrphy_hynix_cfg[] = {
	{DWC_DDRPHYA_MASTER0__DqsPreambleControl_p0, 0x1e3},
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_HYNIX},
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_HYNIX},
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_HYNIX},
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_HYNIX},
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_HYNIX},
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_HYNIX},
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_HYNIX},
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_HYNIX},
	{DWC_DDRPHYA_ANIB0__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX},
	{DWC_DDRPHYA_ANIB1__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX},
	{DWC_DDRPHYA_ANIB2__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX},
	{DWC_DDRPHYA_ANIB3__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX},
	{DWC_DDRPHYA_ANIB4__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX},
	{DWC_DDRPHYA_ANIB5__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX},
	{DWC_DDRPHYA_ANIB6__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX},
	{DWC_DDRPHYA_ANIB7__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX},
	{DWC_DDRPHYA_ANIB8__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX},
	{DWC_DDRPHYA_ANIB9__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX},
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_HYNIX},
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_HYNIX},
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_HYNIX},
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_HYNIX},
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_HYNIX},
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_HYNIX},
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_HYNIX},
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_HYNIX},
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_HYNIX},
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_HYNIX},
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_HYNIX},
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_HYNIX},
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_HYNIX},
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_HYNIX},
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_HYNIX},
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_HYNIX},
	{DWC_DDRPHYA_ANIB0__ATxImpedance, ATxImpedance_LPDDR4_HYNIX},
	{DWC_DDRPHYA_ANIB1__ATxImpedance, ATxImpedance_LPDDR4_HYNIX},
	{DWC_DDRPHYA_ANIB2__ATxImpedance, ATxImpedance_LPDDR4_HYNIX},
	{DWC_DDRPHYA_ANIB3__ATxImpedance, ATxImpedance_LPDDR4_HYNIX},
	{DWC_DDRPHYA_ANIB4__ATxImpedance, ATxImpedance_LPDDR4_HYNIX},
	{DWC_DDRPHYA_ANIB5__ATxImpedance, ATxImpedance_LPDDR4_HYNIX},
	{DWC_DDRPHYA_ANIB6__ATxImpedance, ATxImpedance_LPDDR4_HYNIX},
	{DWC_DDRPHYA_ANIB7__ATxImpedance, ATxImpedance_LPDDR4_HYNIX},
	{DWC_DDRPHYA_ANIB8__ATxImpedance, ATxImpedance_LPDDR4_HYNIX},
	{DWC_DDRPHYA_ANIB9__ATxImpedance, ATxImpedance_LPDDR4_HYNIX},
	{DWC_DDRPHYA_MASTER0__CalDrvStr0, CalDrvStr0_LPDDR4_HYNIX},
};

uint32_t get_sizeof_lpddr4_ddrphy_hynix_cfg(void)
{
	return ARRAY_SIZE(lpddr4_ddrphy_hynix_cfg);
}

struct DRAM_CFG_PARAM lpddr4_ddrphy_samsung_cfg_xg[] = {
	{DWC_DDRPHYA_MASTER0__DqsPreambleControl_p0, 0x1e3},
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_ANIB0__ATxSlewRate, ATxSlewRate_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_ANIB1__ATxSlewRate, ATxSlewRate_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_ANIB2__ATxSlewRate, ATxSlewRate_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_ANIB3__ATxSlewRate, ATxSlewRate_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_ANIB4__ATxSlewRate, ATxSlewRate_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_ANIB5__ATxSlewRate, ATxSlewRate_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_ANIB6__ATxSlewRate, ATxSlewRate_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_ANIB7__ATxSlewRate, ATxSlewRate_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_ANIB8__ATxSlewRate, ATxSlewRate_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_ANIB9__ATxSlewRate, ATxSlewRate_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_ANIB0__ATxImpedance, ATxImpedance_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_ANIB1__ATxImpedance, ATxImpedance_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_ANIB2__ATxImpedance, ATxImpedance_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_ANIB3__ATxImpedance, ATxImpedance_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_ANIB4__ATxImpedance, ATxImpedance_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_ANIB5__ATxImpedance, ATxImpedance_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_ANIB6__ATxImpedance, ATxImpedance_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_ANIB7__ATxImpedance, ATxImpedance_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_ANIB8__ATxImpedance, ATxImpedance_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_ANIB9__ATxImpedance, ATxImpedance_LPDDR4_SAMSUNG_XS32_A1R},
	{DWC_DDRPHYA_MASTER0__CalDrvStr0, CalDrvStr0_LPDDR4_SAMSUNG_XS32_A1R},
};

uint32_t get_sizeof_lpddr4_ddrphy_samsung_cfg_xg(void)
{
	return ARRAY_SIZE(lpddr4_ddrphy_samsung_cfg_xg);
}


struct DRAM_CFG_PARAM lpddr4_ddrphy_hynix_cfg_xh[] = {
	{DWC_DDRPHYA_MASTER0__DqsPreambleControl_p0, 0x1e3},
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_ANIB0__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_ANIB1__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_ANIB2__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_ANIB3__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_ANIB4__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_ANIB5__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_ANIB6__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_ANIB7__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_ANIB8__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_ANIB9__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_ANIB0__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_ANIB1__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_ANIB2__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_ANIB3__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_ANIB4__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_ANIB5__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_ANIB6__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_ANIB7__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_ANIB8__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_ANIB9__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_XH26_B13},
	{DWC_DDRPHYA_MASTER0__CalDrvStr0, CalDrvStr0_LPDDR4_HYNIX},
};

uint32_t get_sizeof_lpddr4_ddrphy_hynix_cfg_xh(void)
{
	return ARRAY_SIZE(lpddr4_ddrphy_hynix_cfg_xh);
}

struct DRAM_CFG_PARAM lpddr4_ddrphy_samsung_cfg_xg36_a17r_2g[] = {
	{DWC_DDRPHYA_MASTER0__DqsPreambleControl_p0, 0x1e3},
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_ANIB0__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_ANIB1__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_ANIB2__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_ANIB3__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_ANIB4__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_ANIB5__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_ANIB6__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_ANIB7__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_ANIB8__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_ANIB9__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_ANIB0__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_ANIB1__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_ANIB2__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_ANIB3__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_ANIB4__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_ANIB5__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_ANIB6__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_ANIB7__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_ANIB8__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_ANIB9__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_XS36_A17R},
	{DWC_DDRPHYA_MASTER0__CalDrvStr0, CalDrvStr0_LPDDR4_HYNIX},
};

uint32_t get_sizeof_lpddr4_ddrphy_samsung_cfg_xg36_a17r_2g(void)
{
	return ARRAY_SIZE(lpddr4_ddrphy_samsung_cfg_xg36_a17r_2g);
}


struct DRAM_CFG_PARAM lpddr4_ddrphy_samsung_cfg_xg32_a1ra_2g[] = {
	{DWC_DDRPHYA_MASTER0__DqsPreambleControl_p0, 0x1e3},
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_ANIB0__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_ANIB1__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_ANIB2__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_ANIB3__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_ANIB4__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_ANIB5__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_ANIB6__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_ANIB7__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_ANIB8__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_ANIB9__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_ANIB0__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_ANIB1__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_ANIB2__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_ANIB3__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_ANIB4__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_ANIB5__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_ANIB6__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_ANIB7__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_ANIB8__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_ANIB9__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_MASTER0__CalDrvStr0, CalDrvStr0_LPDDR4_HYNIX},
};

uint32_t get_sizeof_lpddr4_ddrphy_samsung_cfg_xg32_a1ra_2g(void)
{
	return ARRAY_SIZE(lpddr4_ddrphy_samsung_cfg_xg32_a1ra_2g);
}

struct DRAM_CFG_PARAM lpddr4_ddrphy_samsung_cfg_xg36_a17r[] = {
	{DWC_DDRPHYA_MASTER0__DqsPreambleControl_p0, 0x1e3},
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_ANIB0__ATxSlewRate, ATxSlewRate_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_ANIB1__ATxSlewRate, ATxSlewRate_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_ANIB2__ATxSlewRate, ATxSlewRate_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_ANIB3__ATxSlewRate, ATxSlewRate_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_ANIB4__ATxSlewRate, ATxSlewRate_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_ANIB5__ATxSlewRate, ATxSlewRate_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_ANIB6__ATxSlewRate, ATxSlewRate_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_ANIB7__ATxSlewRate, ATxSlewRate_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_ANIB8__ATxSlewRate, ATxSlewRate_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_ANIB9__ATxSlewRate, ATxSlewRate_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_ANIB0__ATxImpedance, ATxImpedance_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_ANIB1__ATxImpedance, ATxImpedance_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_ANIB2__ATxImpedance, ATxImpedance_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_ANIB3__ATxImpedance, ATxImpedance_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_ANIB4__ATxImpedance, ATxImpedance_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_ANIB5__ATxImpedance, ATxImpedance_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_ANIB6__ATxImpedance, ATxImpedance_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_ANIB7__ATxImpedance, ATxImpedance_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_ANIB8__ATxImpedance, ATxImpedance_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_ANIB9__ATxImpedance, ATxImpedance_LPDDR4_SAMSUNG_XS36_A17R},
	{DWC_DDRPHYA_MASTER0__CalDrvStr0, CalDrvStr0_LPDDR4_SAMSUNG_XS36_A17R},
};

uint32_t get_sizeof_lpddr4_ddrphy_samsung_cfg_xg36_a17r(void)
{
	return ARRAY_SIZE(lpddr4_ddrphy_samsung_cfg_xg36_a17r);
}
struct DRAM_CFG_PARAM lpddr4_ddrphy_hynix_cfg_jh[] = {
	{DWC_DDRPHYA_MASTER0__DqsPreambleControl_p0, 0x1e3},
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_ANIB0__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_ANIB1__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_ANIB2__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_ANIB3__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_ANIB4__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_ANIB5__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_ANIB6__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_ANIB7__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_ANIB8__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_ANIB9__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_ANIB0__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_ANIB1__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_ANIB2__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_ANIB3__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_ANIB4__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_ANIB5__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_ANIB6__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_ANIB7__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_ANIB8__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_ANIB9__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_JH26_A3},
	{DWC_DDRPHYA_MASTER0__CalDrvStr0, CalDrvStr0_LPDDR4_HYNIX},
};

uint32_t get_sizeof_lpddr4_ddrphy_hynix_cfg_jh(void)
{
	return ARRAY_SIZE(lpddr4_ddrphy_hynix_cfg_jh);
}

struct DRAM_CFG_PARAM lpddr4_ddrphy_hynix_cfg_jh32_a1[] = {
	{DWC_DDRPHYA_MASTER0__DqsPreambleControl_p0, 0x1e3},
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_ANIB0__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_ANIB1__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_ANIB2__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_ANIB3__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_ANIB4__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_ANIB5__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_ANIB6__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_ANIB7__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_ANIB8__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_ANIB9__ATxSlewRate, ATxSlewRate_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_ANIB0__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_ANIB1__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_ANIB2__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_ANIB3__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_ANIB4__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_ANIB5__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_ANIB6__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_ANIB7__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_ANIB8__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_ANIB9__ATxImpedance, ATxImpedance_LPDDR4_HYNIX_JH32_A1},
	{DWC_DDRPHYA_MASTER0__CalDrvStr0, CalDrvStr0_LPDDR4_HYNIX},
};

uint32_t get_sizeof_lpddr4_ddrphy_hynix_cfg_jh32_a1(void)
{
	return ARRAY_SIZE(lpddr4_ddrphy_hynix_cfg_jh32_a1);
}

struct DRAM_CFG_PARAM lpddr4_3200_ddrphy_cfg_SAMSUNG_L4S32G2R_JS32_A17RA[] = {
	{DWC_DDRPHYA_MASTER0__DqsPreambleControl_p0, 0x1e3},
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_ANIB0__ATxSlewRate, ATxSlewRate_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_ANIB1__ATxSlewRate, ATxSlewRate_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_ANIB2__ATxSlewRate, ATxSlewRate_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_ANIB3__ATxSlewRate, ATxSlewRate_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_ANIB4__ATxSlewRate, ATxSlewRate_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_ANIB5__ATxSlewRate, ATxSlewRate_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_ANIB6__ATxSlewRate, ATxSlewRate_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_ANIB7__ATxSlewRate, ATxSlewRate_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_ANIB8__ATxSlewRate, ATxSlewRate_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_ANIB9__ATxSlewRate, ATxSlewRate_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_ANIB0__ATxImpedance, ATxImpedance_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_ANIB1__ATxImpedance, ATxImpedance_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_ANIB2__ATxImpedance, ATxImpedance_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_ANIB3__ATxImpedance, ATxImpedance_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_ANIB4__ATxImpedance, ATxImpedance_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_ANIB5__ATxImpedance, ATxImpedance_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_ANIB6__ATxImpedance, ATxImpedance_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_ANIB7__ATxImpedance, ATxImpedance_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_ANIB8__ATxImpedance, ATxImpedance_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_ANIB9__ATxImpedance, ATxImpedance_LPDDR4_SAMSUNG_L4S32G2R_JS32_A17RA},
	{DWC_DDRPHYA_MASTER0__CalDrvStr0, CalDrvStr0_LPDDR4_HYNIX},
};

#define LPDDR4_DDRPHY_PARAM_GERNERATE(SPEED,VENDOR,PARAM, WDQS_EN) \
struct DRAM_CFG_PARAM lpddr4_##SPEED##_ddrphy_cfg_##VENDOR##_##PARAM[] = { \
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_ANIB0__ATxSlewRate, ATxSlewRate_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_ANIB1__ATxSlewRate, ATxSlewRate_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_ANIB2__ATxSlewRate, ATxSlewRate_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_ANIB3__ATxSlewRate, ATxSlewRate_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_ANIB4__ATxSlewRate, ATxSlewRate_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_ANIB5__ATxSlewRate, ATxSlewRate_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_ANIB6__ATxSlewRate, ATxSlewRate_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_ANIB7__ATxSlewRate, ATxSlewRate_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_ANIB8__ATxSlewRate, ATxSlewRate_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_ANIB9__ATxSlewRate, ATxSlewRate_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_MASTER0__PllCtrl2_p0, 0x18},\
	{DWC_DDRPHYA_MASTER0__ARdPtrInitVal_p0, 0x2},\
	{DWC_DDRPHYA_INITENG0__Seq0BGPR4_p0, 0x0},\
	{DWC_DDRPHYA_MASTER0__DqsPreambleControl_p0, WDQS_EN? 0x1E3:0xE3}, /*lpddr4 fix this value, ddr4 need check it, PC: not big issue, but use tested value, so micron change it from 0x1e3 to 0xe3*/ \
	{DWC_DDRPHYA_MASTER0__DbyteDllModeCntrl, 0x2},\
	{DWC_DDRPHYA_MASTER0__DllLockParam_p0, 0x212},\
	{DWC_DDRPHYA_MASTER0__DllGainCtl_p0, 0x61},\
	{DWC_DDRPHYA_MASTER0__ProcOdtTimeCtl_p0, 0x3},\
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_ANIB0__ATxImpedance, ATxImpedance_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_ANIB1__ATxImpedance, ATxImpedance_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_ANIB2__ATxImpedance, ATxImpedance_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_ANIB3__ATxImpedance, ATxImpedance_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_ANIB4__ATxImpedance, ATxImpedance_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_ANIB5__ATxImpedance, ATxImpedance_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_ANIB6__ATxImpedance, ATxImpedance_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_ANIB7__ATxImpedance, ATxImpedance_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_ANIB8__ATxImpedance, ATxImpedance_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_ANIB9__ATxImpedance, ATxImpedance_LPDDR4_##VENDOR##_##PARAM}, \
	{DWC_DDRPHYA_MASTER0__DfiMode, 0x3},\
	{DWC_DDRPHYA_MASTER0__DfiCAMode, 0x4},\
	{DWC_DDRPHYA_MASTER0__CalDrvStr0, CalDrvStr0_LPDDR4_##VENDOR}, \
		{DWC_DDRPHYA_MASTER0__CalVRefs, 0x2},\
	{DWC_DDRPHYA_MASTER0__CalUclkInfo_p0, 0x42b},\
	{DWC_DDRPHYA_MASTER0__CalRate, 0x9},\
	{DWC_DDRPHYA_MASTER0__VrefInGlobal_p0, 0x104},\
	{DWC_DDRPHYA_DBYTE0__DqDqsRcvCntrl_b0_p0, 0x5a1},\
	{DWC_DDRPHYA_DBYTE0__DqDqsRcvCntrl_b1_p0, 0x5a1},\
	{DWC_DDRPHYA_DBYTE1__DqDqsRcvCntrl_b0_p0, 0x5a1},\
	{DWC_DDRPHYA_DBYTE1__DqDqsRcvCntrl_b1_p0, 0x5a1},\
	{DWC_DDRPHYA_DBYTE2__DqDqsRcvCntrl_b0_p0, 0x5a1},\
	{DWC_DDRPHYA_DBYTE2__DqDqsRcvCntrl_b1_p0, 0x5a1},\
	{DWC_DDRPHYA_DBYTE3__DqDqsRcvCntrl_b0_p0, 0x5a1},\
	{DWC_DDRPHYA_DBYTE3__DqDqsRcvCntrl_b1_p0, 0x5a1},\
	{DWC_DDRPHYA_MASTER0__DfiFreqRatio_p0, 0x1},\
	{DWC_DDRPHYA_MASTER0__TristateModeCA_p0, 0x1},\
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat0, 0x0},\
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat1, 0x0},\
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat2, 0x4444},\
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat3, 0x8888},\
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat4, 0x5555},\
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat5, 0x0},\
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat6, 0x0},\
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat7, 0xf000},\
	{DWC_DDRPHYA_DBYTE0__DqDqsRcvCntrl1, 0x500},\
	{DWC_DDRPHYA_DBYTE1__DqDqsRcvCntrl1, 0x500},\
	{DWC_DDRPHYA_DBYTE2__DqDqsRcvCntrl1, 0x500},\
	{DWC_DDRPHYA_DBYTE3__DqDqsRcvCntrl1, 0x500},\
	{DWC_DDRPHYA_MASTER0__MasterX4Config, 0x0},\
	{DWC_DDRPHYA_MASTER0__DMIPinPresent_p0, 0x0},\
	{DWC_DDRPHYA_MASTER0__Acx4AnibDis, 0x0},\
};

LPDDR4_DDRPHY_PARAM_GERNERATE(3200, MICRON, L4M32GR1_M32_A17RA, DISABLE)
LPDDR4_DDRPHY_PARAM_GERNERATE(3200, MICRON, L4M16G_M32_A1RA, ENABLE)
LPDDR4_DDRPHY_PARAM_GERNERATE(3200, MICRON, L4M8GR1_M32_A17R_WDQS, ENABLE)

/* PHY Initialize Configuration */
struct DRAM_CFG_PARAM lpddr4_ddrphy_cfg[] = {
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_MICRON},
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_MICRON},
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_MICRON},
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_MICRON},
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_MICRON},
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_MICRON},
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b0_p0, TxSlewRate_LPDDR4_MICRON},
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b1_p0, TxSlewRate_LPDDR4_MICRON},

	{DWC_DDRPHYA_ANIB0__ATxSlewRate, ATxSlewRate_LPDDR4_MICRON},
	{DWC_DDRPHYA_ANIB1__ATxSlewRate, ATxSlewRate_LPDDR4_MICRON},
	{DWC_DDRPHYA_ANIB2__ATxSlewRate, ATxSlewRate_LPDDR4_MICRON},
	{DWC_DDRPHYA_ANIB3__ATxSlewRate, ATxSlewRate_LPDDR4_MICRON},
	{DWC_DDRPHYA_ANIB4__ATxSlewRate, ATxSlewRate_LPDDR4_MICRON},
	{DWC_DDRPHYA_ANIB5__ATxSlewRate, ATxSlewRate_LPDDR4_MICRON},
	{DWC_DDRPHYA_ANIB6__ATxSlewRate, ATxSlewRate_LPDDR4_MICRON},
	{DWC_DDRPHYA_ANIB7__ATxSlewRate, ATxSlewRate_LPDDR4_MICRON},
	{DWC_DDRPHYA_ANIB8__ATxSlewRate, ATxSlewRate_LPDDR4_MICRON},
	{DWC_DDRPHYA_ANIB9__ATxSlewRate, ATxSlewRate_LPDDR4_MICRON},
	{DWC_DDRPHYA_MASTER0__PllCtrl2_p0, 0x18},
	{DWC_DDRPHYA_MASTER0__ARdPtrInitVal_p0, 0x2},
	{DWC_DDRPHYA_INITENG0__Seq0BGPR4_p0, 0x0},
	{DWC_DDRPHYA_MASTER0__DqsPreambleControl_p0, 0xe3},
	{DWC_DDRPHYA_MASTER0__DbyteDllModeCntrl, 0x2},
	{DWC_DDRPHYA_MASTER0__DllLockParam_p0, 0x212},
	{DWC_DDRPHYA_MASTER0__DllGainCtl_p0, 0x61},
	{DWC_DDRPHYA_MASTER0__ProcOdtTimeCtl_p0, 0x3},
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_MICRON},
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_MICRON},
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_MICRON},
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_MICRON},
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_MICRON},
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_MICRON},
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b0_p0, TxOdtDrvStren_LPDDR4_MICRON},
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b1_p0, TxOdtDrvStren_LPDDR4_MICRON},

	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_MICRON},
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_MICRON},
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_MICRON},
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_MICRON},
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_MICRON},
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_MICRON},
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b0_p0, TxImpedanceCtrl1_LPDDR4_MICRON},
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b1_p0, TxImpedanceCtrl1_LPDDR4_MICRON},

	{DWC_DDRPHYA_ANIB0__ATxImpedance, ATxImpedance_LPDDR4_MICRON},
	{DWC_DDRPHYA_ANIB1__ATxImpedance, ATxImpedance_LPDDR4_MICRON},
	{DWC_DDRPHYA_ANIB2__ATxImpedance, ATxImpedance_LPDDR4_MICRON},
	{DWC_DDRPHYA_ANIB3__ATxImpedance, ATxImpedance_LPDDR4_MICRON},
	{DWC_DDRPHYA_ANIB4__ATxImpedance, ATxImpedance_LPDDR4_MICRON},
	{DWC_DDRPHYA_ANIB5__ATxImpedance, ATxImpedance_LPDDR4_MICRON},
	{DWC_DDRPHYA_ANIB6__ATxImpedance, ATxImpedance_LPDDR4_MICRON},
	{DWC_DDRPHYA_ANIB7__ATxImpedance, ATxImpedance_LPDDR4_MICRON},
	{DWC_DDRPHYA_ANIB8__ATxImpedance, ATxImpedance_LPDDR4_MICRON},
	{DWC_DDRPHYA_ANIB9__ATxImpedance, ATxImpedance_LPDDR4_MICRON},
	{DWC_DDRPHYA_MASTER0__DfiMode, 0x3},
	{DWC_DDRPHYA_MASTER0__DfiCAMode, 0x4},
	{DWC_DDRPHYA_MASTER0__CalDrvStr0, CalDrvStr0_LPDDR4_MICRON},
	{DWC_DDRPHYA_MASTER0__CalVRefs, 0x2},
	{DWC_DDRPHYA_MASTER0__CalUclkInfo_p0, 0x42b},
	{DWC_DDRPHYA_MASTER0__CalRate, 0x9},
	{DWC_DDRPHYA_MASTER0__VrefInGlobal_p0, 0x104},
	{DWC_DDRPHYA_DBYTE0__DqDqsRcvCntrl_b0_p0, 0x5a1},
	{DWC_DDRPHYA_DBYTE0__DqDqsRcvCntrl_b1_p0, 0x5a1},
	{DWC_DDRPHYA_DBYTE1__DqDqsRcvCntrl_b0_p0, 0x5a1},
	{DWC_DDRPHYA_DBYTE1__DqDqsRcvCntrl_b1_p0, 0x5a1},
	{DWC_DDRPHYA_DBYTE2__DqDqsRcvCntrl_b0_p0, 0x5a1},
	{DWC_DDRPHYA_DBYTE2__DqDqsRcvCntrl_b1_p0, 0x5a1},
	{DWC_DDRPHYA_DBYTE3__DqDqsRcvCntrl_b0_p0, 0x5a1},
	{DWC_DDRPHYA_DBYTE3__DqDqsRcvCntrl_b1_p0, 0x5a1},
	{DWC_DDRPHYA_MASTER0__DfiFreqRatio_p0, 0x1},
	{DWC_DDRPHYA_MASTER0__TristateModeCA_p0, 0x1},
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat0, 0x0},
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat1, 0x0},
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat2, 0x4444},
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat3, 0x8888},
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat4, 0x5555},
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat5, 0x0},
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat6, 0x0},
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat7, 0xf000},
	{DWC_DDRPHYA_DBYTE0__DqDqsRcvCntrl1, 0x500},
	{DWC_DDRPHYA_DBYTE1__DqDqsRcvCntrl1, 0x500},
	{DWC_DDRPHYA_DBYTE2__DqDqsRcvCntrl1, 0x500},
	{DWC_DDRPHYA_DBYTE3__DqDqsRcvCntrl1, 0x500},
	{DWC_DDRPHYA_MASTER0__MasterX4Config, 0x0},
	{DWC_DDRPHYA_MASTER0__DMIPinPresent_p0, 0x0},
	{DWC_DDRPHYA_MASTER0__Acx4AnibDis, 0x0},
	#ifdef ENABLE_DDR_CUSTOMER_SETTINGS
	//Add LPDDR4 phy default setting customization here
	#endif
};

uint32_t get_sizeof_lpddr4_ddrphy_cfg(void)
{
	return ARRAY_SIZE(lpddr4_ddrphy_cfg);
}

#define LPDDR4_DDRPHY_FREQS_CFG_P1_DEFAULT \
	/*p1 defult setting same as p0*/ \
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b0_p1, TxSlewRate_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b1_p1, TxSlewRate_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b0_p1, TxSlewRate_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b1_p1, TxSlewRate_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b0_p1, TxSlewRate_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b1_p1, TxSlewRate_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b0_p1, TxSlewRate_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b1_p1, TxSlewRate_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b0_p1, TxOdtDrvStren_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b1_p1, TxOdtDrvStren_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b0_p1, TxOdtDrvStren_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b1_p1, TxOdtDrvStren_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b0_p1, TxOdtDrvStren_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b1_p1, TxOdtDrvStren_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b0_p1, TxOdtDrvStren_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b1_p1, TxOdtDrvStren_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b0_p1, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b1_p1, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b0_p1, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b1_p1, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b0_p1, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b1_p1, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b0_p1, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b1_p1, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE0__DqDqsRcvCntrl_b0_p1, 0x5a1}, \
	{DWC_DDRPHYA_DBYTE0__DqDqsRcvCntrl_b1_p1, 0x5a1}, \
	{DWC_DDRPHYA_DBYTE1__DqDqsRcvCntrl_b0_p1, 0x5a1}, \
	{DWC_DDRPHYA_DBYTE1__DqDqsRcvCntrl_b1_p1, 0x5a1}, \
	{DWC_DDRPHYA_DBYTE2__DqDqsRcvCntrl_b0_p1, 0x5a1}, \
	{DWC_DDRPHYA_DBYTE2__DqDqsRcvCntrl_b1_p1, 0x5a1}, \
	{DWC_DDRPHYA_DBYTE3__DqDqsRcvCntrl_b0_p1, 0x5a1}, \
	{DWC_DDRPHYA_DBYTE3__DqDqsRcvCntrl_b1_p1, 0x5a1}

#define LPDDR4_DDRPHY_FREQS_CFG_P2_DEFAULT \
	/*p2 defult setting same as p0*/ \
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b0_p2, TxSlewRate_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b1_p2, TxSlewRate_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b0_p2, TxSlewRate_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b1_p2, TxSlewRate_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b0_p2, TxSlewRate_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b1_p2, TxSlewRate_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b0_p2, TxSlewRate_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b1_p2, TxSlewRate_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b0_p2, TxOdtDrvStren_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b1_p2, TxOdtDrvStren_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b0_p2, TxOdtDrvStren_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b1_p2, TxOdtDrvStren_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b0_p2, TxOdtDrvStren_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b1_p2, TxOdtDrvStren_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b0_p2, TxOdtDrvStren_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b1_p2, TxOdtDrvStren_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b0_p2, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b1_p2, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b0_p2, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b1_p2, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b0_p2, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b1_p2, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b0_p2, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b1_p2, TxImpedanceCtrl1_LPDDR4_SAMSUNG_XS32_A1R}, \
	{DWC_DDRPHYA_DBYTE0__DqDqsRcvCntrl_b0_p2, 0x5a1}, \
	{DWC_DDRPHYA_DBYTE0__DqDqsRcvCntrl_b1_p2, 0x5a1}, \
	{DWC_DDRPHYA_DBYTE1__DqDqsRcvCntrl_b0_p2, 0x5a1}, \
	{DWC_DDRPHYA_DBYTE1__DqDqsRcvCntrl_b1_p2, 0x5a1}, \
	{DWC_DDRPHYA_DBYTE2__DqDqsRcvCntrl_b0_p2, 0x5a1}, \
	{DWC_DDRPHYA_DBYTE2__DqDqsRcvCntrl_b1_p2, 0x5a1}, \
	{DWC_DDRPHYA_DBYTE3__DqDqsRcvCntrl_b0_p2, 0x5a1}, \
	{DWC_DDRPHYA_DBYTE3__DqDqsRcvCntrl_b1_p2, 0x5a1}

#define LPDDR4_DDRPHY_FREQS_CFG_P1_2666 \
	{DWC_DDRPHYA_MASTER0__ARdPtrInitVal_p1, 0x2}, \
	{DWC_DDRPHYA_INITENG0__Seq0BGPR4_p1, 0x0}, \
	{DWC_DDRPHYA_MASTER0__DqsPreambleControl_p1, 0x1e3}, \
	{DWC_DDRPHYA_MASTER0__DllLockParam_p1, 0x212}, /*change after train*/ \
	{DWC_DDRPHYA_MASTER0__DllGainCtl_p1, 0x61}, /*change after train*/ \
	{DWC_DDRPHYA_MASTER0__ProcOdtTimeCtl_p1, 0x3}, \
	{DWC_DDRPHYA_MASTER0__VrefInGlobal_p1, 0x104}, \
	{DWC_DDRPHYA_MASTER0__DfiFreqRatio_p1, 0x1}, \
	{DWC_DDRPHYA_MASTER0__TristateModeCA_p1, 0x1}, \
	{DWC_DDRPHYA_MASTER0__DMIPinPresent_p1, 0x0}, \
	{DWC_DDRPHYA_MASTER0__PllCtrl2_p1, 0x19}, \
	{DWC_DDRPHYA_MASTER0__ARdPtrInitVal_p1, 0x2}, /*bypass 1 => 2*/ \
	{DWC_DDRPHYA_MASTER0__CalUclkInfo_p1, 0x29b}, \
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat0, 0x6100}, /*3200/2666 ?*/ \
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat4, 0x6655} /*3200/2666 ?*/


#define LPDDR4_DDRPHY_FREQS_CFG_P1_1333 \
	{DWC_DDRPHYA_MASTER0__ARdPtrInitVal_p1, 0x2}, \
	{DWC_DDRPHYA_INITENG0__Seq0BGPR4_p1, 0x0}, \
	{DWC_DDRPHYA_MASTER0__DqsPreambleControl_p1, 0x1e3}, \
	{DWC_DDRPHYA_MASTER0__DllLockParam_p1, 0x212}, /*change after train*/ \
	{DWC_DDRPHYA_MASTER0__DllGainCtl_p1, 0x61}, /*change after train*/ \
	{DWC_DDRPHYA_MASTER0__ProcOdtTimeCtl_p1, 0x3}, \
	{DWC_DDRPHYA_MASTER0__VrefInGlobal_p1, 0x104}, \
	{DWC_DDRPHYA_MASTER0__DfiFreqRatio_p1, 0x1}, \
	{DWC_DDRPHYA_MASTER0__TristateModeCA_p1, 0x1}, \
	{DWC_DDRPHYA_MASTER0__DMIPinPresent_p1, 0x0}, \
	{DWC_DDRPHYA_MASTER0__PllCtrl2_p1, 0x0b}, \
	{DWC_DDRPHYA_MASTER0__ARdPtrInitVal_p1, 0x2}, /*bypass 1 => 2*/ \
	{DWC_DDRPHYA_MASTER0__CalUclkInfo_p1, 0x14d}, \
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat0, 0x6100}, /*3200/2666 ?*/ \
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat4, 0x6655} /*3200/2666 ?*/


#define LPDDR4_DDRPHY_FREQS_CFG_P2_667 \
	{DWC_DDRPHYA_INITENG0__Seq0BGPR4_p2, 0x0}, \
	{DWC_DDRPHYA_MASTER0__DqsPreambleControl_p2, 0x1e3}, \
	{DWC_DDRPHYA_MASTER0__DllLockParam_p2, 0x212},/*change after train*/ \
	{DWC_DDRPHYA_MASTER0__DllGainCtl_p2, 0x61},/*change after train*/ \
	{DWC_DDRPHYA_MASTER0__ProcOdtTimeCtl_p2, 0x3}, \
	{DWC_DDRPHYA_MASTER0__VrefInGlobal_p2, 0x104}, \
	{DWC_DDRPHYA_MASTER0__DfiFreqRatio_p2, 0x1}, \
	{DWC_DDRPHYA_MASTER0__TristateModeCA_p2, 0x1}, \
	{DWC_DDRPHYA_MASTER0__DMIPinPresent_p2, 0x0}, \
	{DWC_DDRPHYA_MASTER0__PllCtrl2_p2, 0x7}, \
	{DWC_DDRPHYA_MASTER0__ARdPtrInitVal_p2, 0x2}, /*bypass 1 => 2*/ \
	{DWC_DDRPHYA_MASTER0__CalUclkInfo_p2, 0xa7}

#define LPDDR4_DDRPHY_FREQS_CFG_P2_333 \
	{DWC_DDRPHYA_INITENG0__Seq0BGPR4_p2, 0x0}, \
	{DWC_DDRPHYA_MASTER0__DqsPreambleControl_p2, 0x1e3}, \
	{DWC_DDRPHYA_MASTER0__DllLockParam_p2, 0x212}, \
	{DWC_DDRPHYA_MASTER0__DllGainCtl_p2, 0x61}, \
	{DWC_DDRPHYA_MASTER0__ProcOdtTimeCtl_p2, 0x3}, \
	{DWC_DDRPHYA_MASTER0__VrefInGlobal_p2, 0x104}, \
	{DWC_DDRPHYA_MASTER0__DfiFreqRatio_p2, 0x1}, \
	{DWC_DDRPHYA_MASTER0__TristateModeCA_p2, 0x1}, \
	{DWC_DDRPHYA_MASTER0__DMIPinPresent_p2, 0x0}, \
	{DWC_DDRPHYA_MASTER0__PllCtrl2_p2, 0x7}, \
	{DWC_DDRPHYA_MASTER0__ARdPtrInitVal_p2, 0x2}, \
	{DWC_DDRPHYA_MASTER0__CalUclkInfo_p2, 0x53}, \
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat0, 0x6600}, \
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat4, 0x6655}

struct DRAM_CFG_PARAM lpddr4_ddrphy_freqs_cfg_2666_667_xg32[] = {
	LPDDR4_DDRPHY_FREQS_CFG_P1_DEFAULT,
	LPDDR4_DDRPHY_FREQS_CFG_P2_DEFAULT,
	LPDDR4_DDRPHY_FREQS_CFG_P1_2666,
	LPDDR4_DDRPHY_FREQS_CFG_P2_667,
	#if (LPDDR4_FFS_6335_FSP==0)
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat0, 0x6600},/*3200/2666/667*/
	#else
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat0, 0x6100},/*3200/2666/667*/
	#endif
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat4, 0x6655}/*3200/2666/667*/
};

struct DRAM_CFG_PARAM lpddr4_ddrphy_freqs_cfg_2666_333_xg32[] = {
	LPDDR4_DDRPHY_FREQS_CFG_P1_DEFAULT,
	LPDDR4_DDRPHY_FREQS_CFG_P2_DEFAULT,
	LPDDR4_DDRPHY_FREQS_CFG_P1_2666,

	//P2 = 333
	{DWC_DDRPHYA_INITENG0__Seq0BGPR4_p2, 0x0},
	{DWC_DDRPHYA_MASTER0__DqsPreambleControl_p2, 0x1e3},
	{DWC_DDRPHYA_MASTER0__DllLockParam_p2, 0x212},//change after train
	{DWC_DDRPHYA_MASTER0__DllGainCtl_p2, 0x61},//change after train
	{DWC_DDRPHYA_MASTER0__ProcOdtTimeCtl_p2, 0x3},

	{DWC_DDRPHYA_MASTER0__VrefInGlobal_p2, 0x104},

	{DWC_DDRPHYA_MASTER0__DfiFreqRatio_p2, 0x1},
	{DWC_DDRPHYA_MASTER0__TristateModeCA_p2, 0x1},
	{DWC_DDRPHYA_MASTER0__DMIPinPresent_p2, 0x0},

	{DWC_DDRPHYA_MASTER0__PllCtrl2_p2, 0x7},
	{DWC_DDRPHYA_MASTER0__ARdPtrInitVal_p2, 0x2}, //bypass 1 => 2
	{DWC_DDRPHYA_MASTER0__CalUclkInfo_p2, 0x53},
	#if (LPDDR4_FFS_6335_FSP==0)
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat0, 0x6600},//3200/2666/333
	#else
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat0, 0x6100},//3200/2666/333
	#endif
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat4, 0x6655},//3200/2666/333
};

struct DRAM_CFG_PARAM lpddr4_ddrphy_freqs_cfg_1333_667_xg26[] = {
        LPDDR4_DDRPHY_FREQS_CFG_P1_DEFAULT,
        LPDDR4_DDRPHY_FREQS_CFG_P2_DEFAULT,
        LPDDR4_DDRPHY_FREQS_CFG_P1_1333,
        LPDDR4_DDRPHY_FREQS_CFG_P2_667,
};

struct DRAM_CFG_PARAM lpddr4_ddrphy_freqs_cfg_1333_333_xg26[] = {
	LPDDR4_DDRPHY_FREQS_CFG_P1_DEFAULT,
	LPDDR4_DDRPHY_FREQS_CFG_P2_DEFAULT,
	LPDDR4_DDRPHY_FREQS_CFG_P1_1333,
	LPDDR4_DDRPHY_FREQS_CFG_P2_333,
};

struct DRAM_CFG_PARAM lpddr4_ddrphy_freqs_cfg_333_jh32_a1ra[] = {
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b0_p1, 0x17F},
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b1_p1, 0x17F},
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b0_p1, 0x17F},
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b1_p1, 0x17F},
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b0_p1, 0x17F},
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b1_p1, 0x17F},
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b0_p1, 0x17F},
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b1_p1, 0x17F},

	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b0_p1, 0x200},
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b1_p1, 0x200},
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b0_p1, 0x200},
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b1_p1, 0x200},
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b0_p1, 0x200},
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b1_p1, 0x200},
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b0_p1, 0x200},
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b1_p1, 0x200},

	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b0_p1, 0xE3F},
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b1_p1, 0xE3F},
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b0_p1, 0xE3F},
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b1_p1, 0xE3F},
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b0_p1, 0xE3F},
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b1_p1, 0xE3F},
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b0_p1, 0xE3F},
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b1_p1, 0xE3F},

	{DWC_DDRPHYA_DBYTE0__DqDqsRcvCntrl_b0_p1, 0x5a1},
	{DWC_DDRPHYA_DBYTE0__DqDqsRcvCntrl_b1_p1, 0x5a1},
	{DWC_DDRPHYA_DBYTE1__DqDqsRcvCntrl_b0_p1, 0x5a1},
	{DWC_DDRPHYA_DBYTE1__DqDqsRcvCntrl_b1_p1, 0x5a1},
	{DWC_DDRPHYA_DBYTE2__DqDqsRcvCntrl_b0_p1, 0x5a1},
	{DWC_DDRPHYA_DBYTE2__DqDqsRcvCntrl_b1_p1, 0x5a1},
	{DWC_DDRPHYA_DBYTE3__DqDqsRcvCntrl_b0_p1, 0x5a1},
	{DWC_DDRPHYA_DBYTE3__DqDqsRcvCntrl_b1_p1, 0x5a1},

	{DWC_DDRPHYA_MASTER0__PllCtrl2_p1, 0x18},
	{DWC_DDRPHYA_MASTER0__ARdPtrInitVal_p1, 0x2},
	{DWC_DDRPHYA_INITENG0__Seq0BGPR4_p1, 0x0},
	{DWC_DDRPHYA_MASTER0__DqsPreambleControl_p1, 0x1e3},
	{DWC_DDRPHYA_MASTER0__DllLockParam_p1, 0x212},//change after train
	{DWC_DDRPHYA_MASTER0__DllGainCtl_p1, 0x61},//change after train
	{DWC_DDRPHYA_MASTER0__ProcOdtTimeCtl_p1, 0x3},

	{DWC_DDRPHYA_MASTER0__CalUclkInfo_p1, 0x53},
	{DWC_DDRPHYA_MASTER0__VrefInGlobal_p1, 0x104},
	{DWC_DDRPHYA_MASTER0__DfiFreqRatio_p1, 0x1},
	{DWC_DDRPHYA_MASTER0__TristateModeCA_p1, 0x1},
	{DWC_DDRPHYA_MASTER0__DMIPinPresent_p1, 0x0},

	{DWC_DDRPHYA_MASTER0__PllCtrl2_p1, 0x7},
	{DWC_DDRPHYA_MASTER0__ARdPtrInitVal_p1, 0x2}, //bypass 1 => 2
	{DWC_DDRPHYA_MASTER0__CalUclkInfo_p1, 0xa7},
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat0, 0x6610}, //2666/333 ?
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat4, 0x6665}, //2666/333 ?
};

struct DRAM_CFG_PARAM lpddr4_ddrphy_freqs_cfg_333_xg32_a1ra_2g[] = {
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b0_p1, TxSlewRate_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b1_p1, TxSlewRate_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b0_p1, TxSlewRate_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b1_p1, TxSlewRate_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b0_p1, TxSlewRate_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b1_p1, TxSlewRate_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b0_p1, TxSlewRate_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b1_p1, TxSlewRate_LPDDR4_HYNIX_L4S16G_XS32_A1RA},

	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b0_p1, TxOdtDrvStren_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b1_p1, TxOdtDrvStren_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b0_p1, TxOdtDrvStren_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b1_p1, TxOdtDrvStren_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b0_p1, TxOdtDrvStren_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b1_p1, TxOdtDrvStren_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b0_p1, TxOdtDrvStren_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b1_p1, TxOdtDrvStren_LPDDR4_HYNIX_L4S16G_XS32_A1RA},

	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b0_p1, TxImpedanceCtrl1_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b1_p1, TxImpedanceCtrl1_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b0_p1, TxImpedanceCtrl1_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b1_p1, TxImpedanceCtrl1_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b0_p1, TxImpedanceCtrl1_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b1_p1, TxImpedanceCtrl1_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b0_p1, TxImpedanceCtrl1_LPDDR4_HYNIX_L4S16G_XS32_A1RA},
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b1_p1, TxImpedanceCtrl1_LPDDR4_HYNIX_L4S16G_XS32_A1RA},

	{DWC_DDRPHYA_DBYTE0__DqDqsRcvCntrl_b0_p1, 0x5a1},
	{DWC_DDRPHYA_DBYTE0__DqDqsRcvCntrl_b1_p1, 0x5a1},
	{DWC_DDRPHYA_DBYTE1__DqDqsRcvCntrl_b0_p1, 0x5a1},
	{DWC_DDRPHYA_DBYTE1__DqDqsRcvCntrl_b1_p1, 0x5a1},
	{DWC_DDRPHYA_DBYTE2__DqDqsRcvCntrl_b0_p1, 0x5a1},
	{DWC_DDRPHYA_DBYTE2__DqDqsRcvCntrl_b1_p1, 0x5a1},
	{DWC_DDRPHYA_DBYTE3__DqDqsRcvCntrl_b0_p1, 0x5a1},
	{DWC_DDRPHYA_DBYTE3__DqDqsRcvCntrl_b1_p1, 0x5a1},

	{DWC_DDRPHYA_MASTER0__PllCtrl2_p1, 0x18},
	{DWC_DDRPHYA_MASTER0__ARdPtrInitVal_p1, 0x2},
	{DWC_DDRPHYA_INITENG0__Seq0BGPR4_p1, 0x0},
	{DWC_DDRPHYA_MASTER0__DqsPreambleControl_p1, 0x1e3},
	{DWC_DDRPHYA_MASTER0__DllLockParam_p1, 0x212},//change after train
	{DWC_DDRPHYA_MASTER0__DllGainCtl_p1, 0x61},//change after train
	{DWC_DDRPHYA_MASTER0__ProcOdtTimeCtl_p1, 0x3},

	{DWC_DDRPHYA_MASTER0__CalUclkInfo_p1, 0x53},
	{DWC_DDRPHYA_MASTER0__VrefInGlobal_p1, 0x104},
	{DWC_DDRPHYA_MASTER0__DfiFreqRatio_p1, 0x1},
	{DWC_DDRPHYA_MASTER0__TristateModeCA_p1, 0x1},
	{DWC_DDRPHYA_MASTER0__DMIPinPresent_p1, 0x0},

	{DWC_DDRPHYA_MASTER0__PllCtrl2_p1, 0x7},
	{DWC_DDRPHYA_MASTER0__ARdPtrInitVal_p1, 0x2}, //bypass 1 => 2
	{DWC_DDRPHYA_MASTER0__CalUclkInfo_p1, 0xa7},
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat0, 0x6610}, //2666/333 ?
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat4, 0x6665}, //2666/333 ?

};


struct DRAM_CFG_PARAM lpddr4_100_ddrphy_cfg[] = {
	{DWC_DDRPHYA_MASTER0__PllCtrl2_p0, 0x7},
	{DWC_DDRPHYA_MASTER0__ARdPtrInitVal_p0, 0x2},
	{DWC_DDRPHYA_MASTER0__ProcOdtTimeCtl_p0, 0xa},
	{DWC_DDRPHYA_MASTER0__CalUclkInfo_p0, 0x19},
	{DWC_DDRPHYA_MASTER0__VrefInGlobal_p0, 0x1bc},
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat0, 0x1666},
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat4, 0x6666},

	{DWC_DDRPHYA_DBYTE0__DFIMRL_p0, 0x5},
	{DWC_DDRPHYA_DBYTE1__DFIMRL_p0, 0x5},
	{DWC_DDRPHYA_DBYTE2__DFIMRL_p0, 0x5},
	{DWC_DDRPHYA_DBYTE3__DFIMRL_p0, 0x5},
	{DWC_DDRPHYA_MASTER0__HwtMRL_p0, 0x5},
	{DWC_DDRPHYA_DBYTE0__TxDqDlyTg0_r0_p0, 0x12},
	{DWC_DDRPHYA_DBYTE0__TxDqDlyTg1_r0_p0, 0x12},
	{DWC_DDRPHYA_DBYTE0__RxEnDlyTg0_u0_p0, 0x147},
	{DWC_DDRPHYA_DBYTE0__RxEnDlyTg1_u0_p0, 0x147},

	{DWC_DDRPHYA_INITENG0__Seq0BGPR1_p0, 0x400},
	{DWC_DDRPHYA_INITENG0__Seq0BGPR2_p0, 0x2},
	{DWC_DDRPHYA_INITENG0__Seq0BGPR3_p0, 0x1000},

	{DWC_DDRPHYA_DBYTE0__PptDqsCntInvTrnTg0_p0, 0x2},
	{DWC_DDRPHYA_DBYTE1__PptDqsCntInvTrnTg0_p0, 0x2},
	{DWC_DDRPHYA_DBYTE2__PptDqsCntInvTrnTg0_p0, 0x2},
	{DWC_DDRPHYA_DBYTE3__PptDqsCntInvTrnTg0_p0, 0x2},
	{DWC_DDRPHYA_DBYTE0__PptDqsCntInvTrnTg1_p0, 0x2},
	{DWC_DDRPHYA_DBYTE1__PptDqsCntInvTrnTg1_p0, 0x2},
	{DWC_DDRPHYA_DBYTE2__PptDqsCntInvTrnTg1_p0, 0x2},
	{DWC_DDRPHYA_DBYTE3__PptDqsCntInvTrnTg1_p0, 0x2},

	{DWC_DDRPHYA_MASTER0__DllGainCtl_p0, 0x20},
	{DWC_DDRPHYA_MASTER0__DllLockParam_p0, 0x1df2},
	#ifdef ENABLE_DDR_CUSTOMER_SETTINGS
	//Add LPDDR4 phy 100 customization here
	#endif
};

uint32_t get_sizeof_lpddr4_100_ddrphy_cfg(void)
{
	return ARRAY_SIZE(lpddr4_100_ddrphy_cfg);
}

/* PHY Initialize Configuration */
struct DRAM_CFG_PARAM lpddr4_667_ddrphy_cfg[] = {
	{DWC_DDRPHYA_MASTER0__PllCtrl2_p0, 0x19},
	{DWC_DDRPHYA_MASTER0__CalUclkInfo_p0, 0xa7},
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat0, 0x1},
	{DWC_DDRPHYA_MASTER0__DfiFreqXlat4, 0x5556},
	#ifdef ENABLE_DDR_CUSTOMER_SETTINGS
	//Add LPDDR4 phy 667 customization here
	#endif
};

uint32_t get_sizeof_lpddr4_667_ddrphy_cfg(void)
{
	return ARRAY_SIZE(lpddr4_667_ddrphy_cfg);
}

struct DRAM_CFG_PARAM lpddr4_2666_ddrphy_cfg[] = {
	{DWC_DDRPHYA_MASTER0__PllCtrl2_p0, 0x19},
	{DWC_DDRPHYA_MASTER0__CalUclkInfo_p0, 0x29b},
	#ifdef ENABLE_DDR_CUSTOMER_SETTINGS
	//Add LPDDR4 phy 2666 customization here
	#endif
};

uint32_t get_sizeof_lpddr4_2666_ddrphy_cfg(void)
{
	return ARRAY_SIZE(lpddr4_2666_ddrphy_cfg);
}

struct DRAM_CFG_PARAM lpddr4_3200_ddrphy_cfg[] = {
	{DWC_DDRPHYA_MASTER0__PllCtrl2_p0, 0x19},
	{DWC_DDRPHYA_MASTER0__CalUclkInfo_p0, 0x320},
	#ifdef ENABLE_DDR_CUSTOMER_SETTINGS
	//Add LPDDR4 phy 3200 customization here
	#endif
};

uint32_t get_sizeof_lpddr4_3200_ddrphy_cfg(void)
{
	return ARRAY_SIZE(lpddr4_3200_ddrphy_cfg);
}

struct DRAM_CFG_PARAM lpddr4_3600_ddrphy_cfg[] = {
	{DWC_DDRPHYA_MASTER0__PllCtrl2_p0, 0x19},
	{DWC_DDRPHYA_MASTER0__CalUclkInfo_p0, 0x384},
	#ifdef ENABLE_DDR_CUSTOMER_SETTINGS
	//Add LPDDR4 phy 3600 customization here
	#endif
};

uint32_t get_sizeof_lpddr4_3600_ddrphy_cfg(void)
{
	return ARRAY_SIZE(lpddr4_3600_ddrphy_cfg);
}

struct DRAM_CFG_PARAM lpddr4_3733_ddrphy_cfg[] = {
	{DWC_DDRPHYA_MASTER0__PllCtrl2_p0, 0x19},
	{DWC_DDRPHYA_MASTER0__CalUclkInfo_p0, 0x320},
	#ifdef ENABLE_DDR_CUSTOMER_SETTINGS
	//Add LPDDR4 phy 3733 customization here
	#endif
};

uint32_t get_sizeof_lpddr4_3733_ddrphy_cfg(void)
{
	return ARRAY_SIZE(lpddr4_3733_ddrphy_cfg);
}

struct DRAM_CFG_PARAM lpddr4x_phy_diff[] = {
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b0_p0, 0x59f},
	{DWC_DDRPHYA_DBYTE0__TxSlewRate_b1_p0, 0x59f},
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b0_p0, 0x59f},
	{DWC_DDRPHYA_DBYTE1__TxSlewRate_b1_p0, 0x59f},
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b0_p0, 0x59f},
	{DWC_DDRPHYA_DBYTE2__TxSlewRate_b1_p0, 0x59f},
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b0_p0, 0x59f},
	{DWC_DDRPHYA_DBYTE3__TxSlewRate_b1_p0, 0x59f},
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b0_p0, 0x600},
	{DWC_DDRPHYA_DBYTE0__TxImpedanceCtrl1_b1_p0, 0x600},
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b0_p0, 0x600},
	{DWC_DDRPHYA_DBYTE1__TxImpedanceCtrl1_b1_p0, 0x600},
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b0_p0, 0x600},
	{DWC_DDRPHYA_DBYTE2__TxImpedanceCtrl1_b1_p0, 0x600},
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b0_p0, 0x600},
	{DWC_DDRPHYA_DBYTE3__TxImpedanceCtrl1_b1_p0, 0x600},
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b0_p0, 0x600},
	{DWC_DDRPHYA_DBYTE0__TxOdtDrvStren_b1_p0, 0x600},
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b0_p0, 0x600},
	{DWC_DDRPHYA_DBYTE1__TxOdtDrvStren_b1_p0, 0x600},
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b0_p0, 0x600},
	{DWC_DDRPHYA_DBYTE2__TxOdtDrvStren_b1_p0, 0x600},
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b0_p0, 0x600},
	{DWC_DDRPHYA_DBYTE3__TxOdtDrvStren_b1_p0, 0x600},
	{DWC_DDRPHYA_MASTER0__CalDrvStr0, 0x00},

	#ifdef ENABLE_DDR_CUSTOMER_SETTINGS
	//Add LPDDR4X phy differet from LPDDR4 customization here
	#endif
};

uint32_t get_sizeof_lpddr4x_phy_diff(void)
{
	return ARRAY_SIZE(lpddr4x_phy_diff);
}

#ifdef SPL_DDR_PKG
extern unsigned int g_ddr_vendor;

void ddr4_ddrp_write_to_bin(char *file, unsigned int freq,
	unsigned int index, unsigned int part_number)
{
	FILE *fp = NULL;
	int ddrp_size = 0, ddrp_freq_size = 0, ddrp_dfs_size = 0;
	int padding_size = 0, i;
	char padding_value = 0;

	fp = fopen(file, "ab+");
	if (NULL == fp) {
		printf("File open fail!\n");
		return ;
	}

	/* ddrc_cfg */
	ddrp_size = sizeof(ddr4_ddrphy_cfg);
	printf("ddr4 ddrc size: %d\n", ddrp_size);
	fwrite(ddr4_ddrphy_cfg, 2, ddrp_size / 2, fp);

	if (g_ddr_vendor == DDR_MANU_SAMSUNG) {
		if(part_number == K4A4G165WF_BCTD) {
			if (freq == DDR_FREQC_2400) {
				ddrp_size = ddrp_size + sizeof(ddr4_ddrphy_cfg_SAMSUNG_D4S512M_S24_A3);
				fwrite(ddr4_ddrphy_cfg_SAMSUNG_D4S512M_S24_A3, 2, sizeof(ddr4_ddrphy_cfg_SAMSUNG_D4S512M_S24_A3) / 2, fp);
			} else if (freq == DDR_FREQC_2640) {
				ddrp_size = ddrp_size + sizeof(ddr4_ddrphy_cfg_SAMSUNG_D4S512M_S2640_A3);
				fwrite(ddr4_ddrphy_cfg_SAMSUNG_D4S512M_S2640_A3, 2, sizeof(ddr4_ddrphy_cfg_SAMSUNG_D4S512M_S2640_A3) / 2, fp);
			}

		} else {
			ddrp_size = ddrp_size + sizeof(ddr4_ddrphy_samsung_cfg);
			fwrite(ddr4_ddrphy_samsung_cfg, 2,
				sizeof(ddr4_ddrphy_samsung_cfg) / 2, fp);
		}
	}

	/* ddrc_freq */
	if (freq == DDR_FREQC_3200) {
		ddrp_freq_size = sizeof(ddr4_3200_ddrphy_cfg);
		fwrite(ddr4_3200_ddrphy_cfg, 2, ddrp_freq_size / 2, fp);
	} else if (freq == DDR_FREQC_2666) {
		ddrp_freq_size = sizeof(ddr4_2666_ddrphy_cfg);
		fwrite(ddr4_2666_ddrphy_cfg, 2, ddrp_freq_size / 2, fp);
	} else if (freq == DDR_FREQC_2640) {
		ddrp_freq_size = sizeof(ddr4_2640_ddrphy_cfg);
		fwrite(ddr4_2640_ddrphy_cfg, 2, ddrp_freq_size / 2, fp);
	} else if (freq == DDR_FREQC_2400) {
		ddrp_freq_size = sizeof(ddr4_2400_ddrphy_cfg);
		fwrite(ddr4_2400_ddrphy_cfg, 2, ddrp_freq_size / 2, fp);
	} else if (freq == DDR_FREQC_1600) {
		ddrp_freq_size = sizeof(ddr4_1600_ddrphy_cfg);
		fwrite(ddr4_1600_ddrphy_cfg, 2, ddrp_freq_size / 2, fp);
	}

	/* align 512 */
	ddrp_size = ddrp_size + ddrp_freq_size;
	if (ddrp_size % 512)
		padding_size = 512 - ((ddrp_size % 512));

	for (i = 0; i < padding_size; i++) {
		fwrite(&padding_value, 1, 1, fp);
	}

	hdr_uart.ddr_ddrp.addr = hdr_uart.ddr_ddrc.addr +
		ALIGN_512(hdr_uart.ddr_ddrc.size);
	hdr_uart.ddr_ddrp.size = ddrp_size;

	hdr_ddr.ddr[index].ddr_ddrp.addr = hdr_ddr.ddr[index].ddr_ddrc_freqs.addr +
		ALIGN_512(hdr_ddr.ddr[index].ddr_ddrc_freqs.size);
	hdr_ddr.ddr[index].ddr_ddrp.size = ddrp_size;
	/*dfs ddr_ddrc_freqs*/
	hdr_ddr.ddr[index].ddr_ddrp_freqs.addr = hdr_ddr.ddr[index].ddr_ddrp.addr +
		ALIGN_512(hdr_ddr.ddr[index].ddr_ddrp.size);
	hdr_ddr.ddr[index].ddr_ddrp_freqs.size = ddrp_dfs_size;

	pclose(fp);
	return;
}

void lpddr4_ddrp_micron_write_to_bin(char *file, unsigned int freq,
	unsigned int index, unsigned int part_number, unsigned int alter_para)
{
	FILE *fp = NULL;
	int ddrp_size = 0, ddrp_micron_size = 0, ddrp_freq_size = 0, ddrp_dfs_size = 0, ddrp_type_size = 0;
	int padding_size = 0, i;
	char padding_value = 0;

	fp = fopen(file, "ab+");
	if (NULL == fp) {
		printf("File open fail!\n");
		return ;
	}

	/* ddrc_cfg */
	//ddrp_size = sizeof(lpddr4_ddrphy_cfg);
	//fwrite(lpddr4_ddrphy_cfg, 2, ddrp_size / 2, fp);
	/* ddrc_micron_cfg */
	if (freq == DDR_FREQC_3733) {
	} else if (freq == DDR_FREQC_3200) {
		if (part_number == MT53E1G32D2FW_046AUTA) {
			ddrp_micron_size = sizeof(lpddr4_3200_ddrphy_cfg_MICRON_L4M32GR1_M32_A17RA);
			fwrite(lpddr4_3200_ddrphy_cfg_MICRON_L4M32GR1_M32_A17RA, 2, ddrp_micron_size / 2, fp);
		} else if (part_number == MT53D512M32D2DT_046AAT) { //Inceptio
			ddrp_micron_size = sizeof(lpddr4_3200_ddrphy_cfg_MICRON_L4M16G_M32_A1RA);
			fwrite(lpddr4_3200_ddrphy_cfg_MICRON_L4M16G_M32_A1RA, 2, ddrp_micron_size / 2, fp);
		}  else if (MT53E256M32D2DS_053AAT == part_number) {
			ddrp_micron_size = sizeof(lpddr4_3200_ddrphy_cfg_MICRON_L4M8GR1_M32_A17R_WDQS);
			fwrite(lpddr4_3200_ddrphy_cfg_MICRON_L4M8GR1_M32_A17R_WDQS, 2, ddrp_micron_size / 2, fp);
		}
	} else if (freq == DDR_FREQC_2666) {
		if (part_number == MT53D1024M32D4DT) {
			ddrp_size = sizeof(lpddr4_ddrphy_cfg);
			fwrite(lpddr4_ddrphy_cfg, 2, ddrp_size / 2, fp);
		}
	} else if (freq == DDR_FREQC_667) {
	} else if (freq == DDR_FREQC_100) {
		ddrp_size = sizeof(lpddr4_ddrphy_cfg);
		fwrite(lpddr4_ddrphy_cfg, 2, ddrp_size / 2, fp);
	}

	/* ddrc_freq */
	if (freq == DDR_FREQC_3733) {
		ddrp_freq_size = sizeof(lpddr4_3733_ddrphy_cfg);
		fwrite(lpddr4_3733_ddrphy_cfg, 2, ddrp_freq_size / 2, fp);
	} else if (freq == DDR_FREQC_3200) {
		ddrp_freq_size = sizeof(lpddr4_3200_ddrphy_cfg);
		fwrite(lpddr4_3200_ddrphy_cfg, 2, ddrp_freq_size / 2, fp);
	} else if (freq == DDR_FREQC_2666) {
		ddrp_freq_size = sizeof(lpddr4_2666_ddrphy_cfg);
		fwrite(lpddr4_2666_ddrphy_cfg, 2, ddrp_freq_size / 2, fp);
	} else if (freq == DDR_FREQC_667) {
		ddrp_freq_size = sizeof(lpddr4_667_ddrphy_cfg);
		fwrite(lpddr4_667_ddrphy_cfg, 2, ddrp_freq_size / 2, fp);
	} else if (freq == DDR_FREQC_100) {
		ddrp_freq_size = sizeof(lpddr4_100_ddrphy_cfg);
		fwrite(lpddr4_100_ddrphy_cfg, 2, ddrp_freq_size / 2, fp);
	}

	/* align 512 */
	ddrp_size = ddrp_size + ddrp_micron_size + ddrp_freq_size + ddrp_type_size;
	if (ddrp_size % 512)
		padding_size = 512 - ((ddrp_size % 512));

	for (i = 0; i < padding_size; i++) {
		fwrite(&padding_value, 1, 1, fp);
	}
	printf("lpddr4 micron ddrp padding size = %d\n", padding_size);

	hdr_uart.ddr_ddrp.addr = hdr_uart.ddr_ddrc.addr +
		ALIGN_512(hdr_uart.ddr_ddrc.size);
	hdr_uart.ddr_ddrp.size = ddrp_size;

	hdr_ddr.ddr[index].ddr_ddrp.addr = hdr_ddr.ddr[index].ddr_ddrc_freqs.addr +
		ALIGN_512(hdr_ddr.ddr[index].ddr_ddrc_freqs.size);
	hdr_ddr.ddr[index].ddr_ddrp.size = ddrp_size;
	/*dfs ddr_ddrc_freqs*/
	hdr_ddr.ddr[index].ddr_ddrp_freqs.addr = hdr_ddr.ddr[index].ddr_ddrp.addr +
		ALIGN_512(hdr_ddr.ddr[index].ddr_ddrp.size);
	hdr_ddr.ddr[index].ddr_ddrp_freqs.size = ddrp_dfs_size;

	pclose(fp);
	return;
}

void lpddr4_ddrp_hynix_write_to_bin(char *file, unsigned int freq,
	unsigned int index, unsigned int part_number, unsigned int alter_para)
{
	FILE *fp = NULL;
	int ddrp_size = 0, ddrp_hynix_size = 0, ddrp_freq_size = 0, ddrp_dfs_size = 0;
	int padding_size = 0, i;
	char padding_value = 0;
	int32_t tmp_dfs_size = 0;

	fp = fopen(file, "ab+");
	if (NULL == fp) {
		printf("File open fail!\n");
		return ;
	}

	/* ddrc_cfg */
	ddrp_size = sizeof(lpddr4_ddrphy_cfg);
	fwrite(lpddr4_ddrphy_cfg, 2, ddrp_size / 2, fp);

	/* ddrc_hynix_cfg */
	if (part_number == H9HCNNN8KUMLHR) {
		ddrp_hynix_size = sizeof(lpddr4_ddrphy_hynix_cfg_xh);
		fwrite(lpddr4_ddrphy_hynix_cfg_xh, 2, ddrp_hynix_size / 2, fp);
	} else if (part_number == H9HCNNNBKUMLHR) {
		if (freq == DDR_FREQC_3200) {
			ddrp_hynix_size = sizeof(lpddr4_ddrphy_hynix_cfg_jh32_a1);
			fwrite(lpddr4_ddrphy_hynix_cfg_jh32_a1, 2, ddrp_hynix_size / 2, fp);
		} else {
			ddrp_hynix_size = sizeof(lpddr4_ddrphy_hynix_cfg_jh);
			fwrite(lpddr4_ddrphy_hynix_cfg_jh, 2, ddrp_hynix_size / 2, fp);
		}
	} else {
		ddrp_hynix_size = sizeof(lpddr4_ddrphy_hynix_cfg);
		fwrite(lpddr4_ddrphy_hynix_cfg, 2, ddrp_hynix_size / 2, fp);
	}

	/* ddrc_freq */
	if (freq == DDR_FREQC_3733) {
		ddrp_freq_size = sizeof(lpddr4_3733_ddrphy_cfg);
		fwrite(lpddr4_3733_ddrphy_cfg, 2, ddrp_freq_size / 2, fp);
	} else if (freq == DDR_FREQC_3200) {
		ddrp_freq_size = sizeof(lpddr4_3200_ddrphy_cfg);
		fwrite(lpddr4_3200_ddrphy_cfg, 2, ddrp_freq_size / 2, fp);
	} else if (freq == DDR_FREQC_2666) {
		ddrp_freq_size = sizeof(lpddr4_2666_ddrphy_cfg);
		fwrite(lpddr4_2666_ddrphy_cfg, 2, ddrp_freq_size / 2, fp);
	} else if (freq == DDR_FREQC_667) {
		ddrp_freq_size = sizeof(lpddr4_667_ddrphy_cfg);
		fwrite(lpddr4_667_ddrphy_cfg, 2, ddrp_freq_size / 2, fp);
	}

	/* align 512 */
	ddrp_size = ddrp_size + ddrp_hynix_size + ddrp_freq_size;
	if (ddrp_size % 512)
		padding_size = 512 - ((ddrp_size % 512));

	for (i = 0; i < padding_size; i++) {
		fwrite(&padding_value, 1, 1, fp);
	}

	printf("lpddr4 hynix ddrp size: %d\n", ddrp_size);
	printf("lpddr4 hynix ddrp padding size = %d\n", padding_size);

	hdr_uart.ddr_ddrp.addr = hdr_uart.ddr_ddrc.addr +
		ALIGN_512(hdr_uart.ddr_ddrc.size);
	hdr_uart.ddr_ddrp.size = ddrp_size;

	if (freq == DDR_FREQC_3200) {
			if (part_number == H9HCNNNBKUMLHR) {
			tmp_dfs_size = LPDDR4_FREQS_CFG_ADD(DDR_FREQC_3200,
							    DDR_FREQC_333,
							    0,
							    lpddr4_ddrphy_freqs_cfg_333_jh32_a1ra,
							    lpddr4_3200_333,
							    lpddr4_3200_333_cnt);
			if (tmp_dfs_size > 0)
				ddrp_dfs_size = tmp_dfs_size;
		}
	}
	hdr_ddr.ddr[index].ddr_ddrp.addr = hdr_ddr.ddr[index].ddr_ddrc_freqs.addr +
		ALIGN_512(hdr_ddr.ddr[index].ddr_ddrc_freqs.size);
	hdr_ddr.ddr[index].ddr_ddrp.size = ddrp_size;
	/*dfs ddr_ddrc_freqs*/
	hdr_ddr.ddr[index].ddr_ddrp_freqs.addr = hdr_ddr.ddr[index].ddr_ddrp.addr +
		ALIGN_512(hdr_ddr.ddr[index].ddr_ddrp.size);
	hdr_ddr.ddr[index].ddr_ddrp_freqs.size = ddrp_dfs_size;

	pclose(fp);
	return;
}

void lpddr4_ddrp_samsung_write_to_bin(char *file, unsigned int freq,
	unsigned int index, unsigned int part_number, unsigned int alter_para)
{
	FILE *fp = NULL;
	int ddrp_size = 0, ddrp_samsung_size = 0 ,ddrp_freq_size = 0, ddrp_dfs_size = 0;
	int32_t tmp_dfs_size = 0;
	int padding_size = 0, i;
	char padding_value = 0;

	fp = fopen(file, "ab+");
	if (NULL == fp) {
		printf("File open fail!\n");
		return ;
	}

	/* ddrc_cfg */
	ddrp_size = sizeof(lpddr4_ddrphy_cfg);
	fwrite(lpddr4_ddrphy_cfg, 2, ddrp_size / 2, fp);
        /* ddrc_hynix_cfg */
        if (part_number == K4F8E304HBMGCJ) {
		if (freq == DDR_FREQC_3600) {
			/*XG36 1G A17R*/
			ddrp_samsung_size = sizeof(lpddr4_ddrphy_samsung_cfg_xg36_a17r);
			fwrite(lpddr4_ddrphy_samsung_cfg_xg36_a17r, 2, ddrp_samsung_size / 2, fp);
		} else {
			ddrp_samsung_size = sizeof(lpddr4_ddrphy_samsung_cfg_xg);
			fwrite(lpddr4_ddrphy_samsung_cfg_xg, 2, ddrp_samsung_size / 2, fp);
		}
	} else if (part_number == K4F6E3S4HMMGCJ) {
		if (freq == DDR_FREQC_3600) {
			/*XG36 2G A17R */
			ddrp_samsung_size = sizeof(lpddr4_ddrphy_samsung_cfg_xg36_a17r_2g);
			fwrite(lpddr4_ddrphy_samsung_cfg_xg36_a17r_2g, 2, ddrp_samsung_size / 2, fp);
		} else if (freq == DDR_FREQC_3200) {
                        ddrp_samsung_size = sizeof(lpddr4_ddrphy_samsung_cfg_xg32_a1ra_2g);
			fwrite(lpddr4_ddrphy_samsung_cfg_xg32_a1ra_2g, 2, ddrp_samsung_size / 2, fp);
		}
	} else if(K4FBE3D4HM_THCL == part_number) {
		if (DDR_FREQC_3200 == freq) {
			ddrp_samsung_size = sizeof(lpddr4_3200_ddrphy_cfg_SAMSUNG_L4S32G2R_JS32_A17RA);
			fwrite(lpddr4_3200_ddrphy_cfg_SAMSUNG_L4S32G2R_JS32_A17RA, 2, ddrp_samsung_size / 2, fp);
		}
	} else {
                ddrp_samsung_size = sizeof(lpddr4_ddrphy_hynix_cfg);
                fwrite(lpddr4_ddrphy_hynix_cfg, 2, ddrp_samsung_size / 2, fp);
        }

	/* ddrp_freq */
	if (freq == DDR_FREQC_3733) {
		ddrp_freq_size = sizeof(lpddr4_3733_ddrphy_cfg);
		fwrite(lpddr4_3733_ddrphy_cfg, 2, ddrp_freq_size / 2, fp);
	} else if (freq == DDR_FREQC_3600) {
		ddrp_freq_size = sizeof(lpddr4_3600_ddrphy_cfg);
		fwrite(lpddr4_3600_ddrphy_cfg, 2, ddrp_freq_size / 2, fp);
	} else if (freq == DDR_FREQC_3200) {
		ddrp_freq_size = sizeof(lpddr4_3200_ddrphy_cfg);
		fwrite(lpddr4_3200_ddrphy_cfg, 2, ddrp_freq_size / 2, fp);
	} else if (freq == DDR_FREQC_2666) {
		ddrp_freq_size = sizeof(lpddr4_2666_ddrphy_cfg);
		fwrite(lpddr4_2666_ddrphy_cfg, 2, ddrp_freq_size / 2, fp);
	} else if (freq == DDR_FREQC_667) {
		ddrp_freq_size = sizeof(lpddr4_667_ddrphy_cfg);
		fwrite(lpddr4_667_ddrphy_cfg, 2, ddrp_freq_size / 2, fp);
	}

	/* align 512 */
	ddrp_size = ddrp_size + ddrp_samsung_size + ddrp_freq_size;
	if (ddrp_size % 512)
		padding_size = 512 - ((ddrp_size % 512));

	for (i = 0; i < padding_size; i++) {
		fwrite(&padding_value, 1, 1, fp);
	}

	printf("lpddr4 samsung ddrp size: %d\n", ddrp_size);
#ifdef YMODEM_BOOT
#else
	printf("lpddr4 samsung ddrp padding size = %d\n", padding_size);
	if (part_number == K4F8E304HBMGCJ && freq == DDR_FREQC_3200) {
		tmp_dfs_size = LPDDR4_FREQS_CFG_ADD(DDR_FREQC_3200,
						    DDR_FREQC_2666,
						    DDR_FREQC_667,
						    lpddr4_ddrphy_freqs_cfg_2666_667_xg32,
						    lpddr4_samsung_1g,
						    lpddr4_samsung_1g_cnt);
		if (tmp_dfs_size > 0)
			ddrp_dfs_size = tmp_dfs_size;
		tmp_dfs_size = LPDDR4_FREQS_CFG_ADD(DDR_FREQC_3200,
						    DDR_FREQC_2666,
						    DDR_FREQC_333,
						    lpddr4_ddrphy_freqs_cfg_2666_333_xg32,
						    lpddr4_samsung_1g,
						    lpddr4_samsung_1g_cnt);
		if (tmp_dfs_size > 0)
			ddrp_dfs_size = tmp_dfs_size;

		tmp_dfs_size = LPDDR4_FREQS_CFG_ADD(DDR_FREQC_3200,
						    DDR_FREQC_1333,
						    DDR_FREQC_333,
						    //phy setting of p1&p2 is the same as p0=2666
						    lpddr4_ddrphy_freqs_cfg_1333_333_xg26,
						    lpddr4_samsung_1g,
						    lpddr4_samsung_1g_cnt);
		if (tmp_dfs_size > 0)
			ddrp_dfs_size = tmp_dfs_size;
	}
	if (part_number == K4F8E304HBMGCJ && freq == DDR_FREQC_2666) {
		tmp_dfs_size = LPDDR4_FREQS_CFG_ADD(DDR_FREQC_2666,
						    DDR_FREQC_1333,
						    DDR_FREQC_667,
						    lpddr4_ddrphy_freqs_cfg_1333_667_xg26,
						    lpddr4_samsung_1g,
						    lpddr4_samsung_1g_cnt);
		if (tmp_dfs_size > 0)
			ddrp_dfs_size = tmp_dfs_size;
		tmp_dfs_size = LPDDR4_FREQS_CFG_ADD(DDR_FREQC_2666,
						    DDR_FREQC_1333,
						    DDR_FREQC_333,
						    lpddr4_ddrphy_freqs_cfg_1333_333_xg26,
						    lpddr4_samsung_1g,
						    lpddr4_samsung_1g_cnt);
		if (tmp_dfs_size > 0)
			ddrp_dfs_size = tmp_dfs_size;
	}
	if (part_number == K4F6E3S4HMMGCJ && freq == DDR_FREQC_3200) {
		tmp_dfs_size = LPDDR4_FREQS_CFG_ADD(DDR_FREQC_3200,
				DDR_FREQC_1333,
				DDR_FREQC_333,
				lpddr4_ddrphy_freqs_cfg_1333_333_xg26,
				lpddr4_samsung_2g,
				lpddr4_samsung_2g_cnt);
		if (tmp_dfs_size > 0)
			ddrp_dfs_size = tmp_dfs_size;
	}
#endif

	hdr_uart.ddr_ddrp.addr = hdr_uart.ddr_ddrc.addr +
		ALIGN_512(hdr_uart.ddr_ddrc.size);
	hdr_uart.ddr_ddrp.size = ddrp_size;

	hdr_ddr.ddr[index].ddr_ddrp.addr = hdr_ddr.ddr[index].ddr_ddrc_freqs.addr +
		ALIGN_512(hdr_ddr.ddr[index].ddr_ddrc_freqs.size);
	hdr_ddr.ddr[index].ddr_ddrp.size = ddrp_size;
	/*dfs ddr_ddrc_freqs*/
	hdr_ddr.ddr[index].ddr_ddrp_freqs.addr = hdr_ddr.ddr[index].ddr_ddrp.addr +
		ALIGN_512(hdr_ddr.ddr[index].ddr_ddrp.size);
	hdr_ddr.ddr[index].ddr_ddrp_freqs.size = ddrp_dfs_size;

	pclose(fp);
	return;
}


#endif
